This invention generally relates to microprocessors, and more specifically to improvements in direct memory access circuits, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a digital system with a multi-channel direct memory access (DMA) controller, wherein the DMA controller comprises a plurality of channel circuits each having at least one channel address output node for providing a channel address and at least one request output; and a plurality of port circuits each having a plurality of channel address input nodes connected to a respective channel address output node of the plurality of channel circuits, each port circuit of the plurality of port circuits having a memory address output node for providing a channel address selected from the plurality of address input nodes to a respective associated memory resource. Each port has a scheduler circuit connected to the request outputs on the plurality of channel circuits. The scheduler circuit is operable to select the next request that will be served by the port, such that the plurality of port circuits are operable to access the respective associated memory resources simultaneously.
In accordance with another aspect of the present invention, each channel circuit has a FIFO buffer and at least one of the port circuits is operable to perform a burst transfer of data between the FIFO buffer of a selected channel circuit and the memory circuit associated with the at least one port circuit.
In accordance with another aspect of the present invention, each channel circuit has a read address circuit and a separate write channel address circuit. There is a separate bus connected from each read address circuit to the respective channel address input nodes of the plurality of port circuits and a separate bus connected from each write address circuit to the Cross Reference to Related Applications respective channel address input nodes of the plurality of port circuits.
In accordance with another aspect of the present invention, a method of operating a digital system comprising a microprocessor, wherein the microprocessor is connected to a multi-channel direct memory access circuit having a plurality of channel circuits and a plurality of port circuits each connected to a memory resource for transferring data words, is provided. A plurality pending transfer requests with transfer addresses is generated simultaneously in the channel circuits. All of the pending transfer requests are provided to each of the plurality of port circuits. Each port is scheduled individually by selecting a transfer request and a channel from among the pending transfer requests. A data transfer is performed between each port and the selected channel such that all of the plurality of ports transfer a requested data word on the same clock cycle.